cpu - Verilog: Store bits into a specific range of bits of an initialized module -

so have been following guide provided embeddedmicro on producing simple 16 bit cpu using hdl lucid. goal convert on verilog in quartus ii. problem having trying store bits allocated destination of data specific range of bits inside designated register. second problem having using global constant 1 of case values. able around replacing constant value. have added include file project settings. still new verilog might abundant of bad code.

the error recieved on line 57

    shift_r.d[dest] = din; //supposed storing data coming in register 

error readout: verilog syntax error, near text: "=". check , fix syntax errors appear before or @ specified keyword

`include "cpu_8/my_incl.vh"   module cpu(clk,rst,write,read,address,dout,din); input rst,clk; input [0:7] din; //data in output reg [0:7] address; output reg [0:7] dout; //data out output reg write,read;  reg [0:15] inst;    //i not sure if set array registers correctly either shiftreg shift_r[0:15] (rst, clk, d, q); //initialize shift_r , create array of 16 registers. //implicit net created d , q above when generating block file   instrom_16 instroms(address, inst); //intialize instrom_16 module    reg [0:3]op;        // opcode reg [0:3]arg1;      // first arg reg [0:3]arg2;      // second arg reg [0:3]dest;      // destination arg reg [0:7]constant;  //constant    always@(posedge clk) begin     write = 0;      // don't write     read  = 0;       // don't read     address = 8'b0; // don't care     dout = 8'b0;    // don't care      instroms.address = shift_r.d[0]; //set shift_reg program counter     shift_r.d = shift_r.q[0] + 1;   //increment program counter.         op = instroms.inst[15:12]; // opcode first 4 bits     dest = instroms.inst[11:8]; // destination 1 4 bits     arg1 = instroms.inst[7:4]; // argument2 next 4 bits     arg2 = instroms.inst[3:0];  // argument2 last 4 bits     constant = instroms.inst[7:0];      //perform operations         case (op)             4'd1: //tried use `load wouldn't point value in include file                 read = 1;                                 // request read                  //line failing                 shift_r.d[dest] = din; //supposed storing data coming in register           //4'd2:       endcase      end   endmodule 

this include file

`ifndef _my_incl_vh_ `define _my_incl_vh_  `define nop   = 4'd0;  // 0 filled  `define load  = 4'd1; // load  `endif 

you made little mistake: shiftreg shift_r[0:15] (rst, clk, d, q);

instantiates array of shift_r, each instance of has rst, clk, d , q.

so shift_r.d[dest} should become shift_r[dest].d , shift_r.q[0] should become shift_r[0].q.

for shift_r.d, guess want 0:15 vector. need assign 16 bits intermediate wire of 15 bits using e.g. loop.

hope helps